forked from W4D/soundcube-firmware
Codec ok, transients are quite rounded. Maybe hardware, maybe codec settings.
This commit is contained in:
@ -14,18 +14,14 @@ int16_t volume = 0;
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size_t count;
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size_t count;
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void codec_transmit() {
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void codec_transmit() {
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for(int i = 0; i < count; i++){
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buffer[i] *= -1;
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}
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i2s.write((const uint8_t *)&buffer, count * sizeof(int16_t));
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i2s.write((const uint8_t *)&buffer, count * sizeof(int16_t));
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}
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}
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void codec_receive(){
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void codec_receive(){
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count = i2s.read((uint8_t *)&buffer, SIZE * sizeof(int16_t)) * sizeof(uint32_t) / sizeof(int16_t);
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count = i2s.read((uint8_t *)&buffer, SIZE * sizeof(int16_t)) * sizeof(uint32_t) / sizeof(int16_t);
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size_t index = 0;
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volume = 0;
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while (index < count) {
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volume += buffer[index];
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buffer[index] = 0;
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index++;
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}
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}
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}
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void cw(unsigned char first, unsigned char second){
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void cw(unsigned char first, unsigned char second){
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@ -95,18 +91,20 @@ void setup() {
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// POWER and CM
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// POWER and CM
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cw(0x00, 0x01); // select page 1
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cw(0x00, 0x01); // select page 1
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cw(0x01, 0x08); // disable weak (crude) AVdd connection to DVdd
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cw(0x01, 0b00001000); // disable weak (crude) AVdd connection to DVdd
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cw(0x02, 0x01); // enable internal AVdd LDO and enable analog blocks
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cw(0x02, 0b00000001); // enable internal AVdd LDO and enable analog blocks
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cw(0x09, 0b00001100); // power up LOL, LOR, power down MAL, MAR, HPL, HPR
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cw(0x09, 0b00001100); // power up LOL, LOR, power down MAL, MAR, HPL, HPR
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cw(0x0a, 0b01000000); // set full chip CM to 0.75V
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cw(0x0a, 0b00001000); // set full chip CM to 0.75V
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cw(0x47, 0b00110010); // analog input quick charge time 6.4ms
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cw(0x47, 0b00110011); // analog input quick charge time 1.6ms
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// ROUTING
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// ROUTING
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cw(0x00, 0x01); // select page 1
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cw(0x00, 0x01); // select page 1
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cw(0x34, 0b11000000); // LEFT MICPGA P route IN1L to LEFT_P with 40k input impedance
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cw(0x34, 0b11000000); // LEFT MICPGA P route IN1L to LEFT_P with 40k input impedance
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cw(0x36, 0b11000000); // LEFT MICPGA M route CM to LEFT_M with 20k input impedance
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cw(0x36, 0b11000000); // LEFT MICPGA M route CM to LEFT_M with 20k input impedance
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//cw(0x36, 0b00000011); // LEFT MICPGA M route CM to LEFT_M with 20k input impedance
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cw(0x37, 0b11000000); // RIGHT MICPGA P route IN1R to RIGHT_P with 20k input impedance
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cw(0x37, 0b11000000); // RIGHT MICPGA P route IN1R to RIGHT_P with 20k input impedance
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cw(0x39, 0b11000000); // RIGHT MICPGA M route CM to RIGHT_M with 20k input impedance
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cw(0x39, 0b11000000); // RIGHT MICPGA M route CM to RIGHT_M with 20k input impedance
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//cw(0x39, 0b00000011); // RIGHT MICPGA M route CM to RIGHT_M with 20k input impedance
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cw(0x3a, 0b00111100); // connect IN2, IN3 weakly to CM
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cw(0x3a, 0b00111100); // connect IN2, IN3 weakly to CM
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// GAIN
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// GAIN
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@ -123,11 +121,12 @@ void setup() {
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cw(0x00, 0x00); // select page 0
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cw(0x00, 0x00); // select page 0
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cw(0x12, 0x81); // NADC 1
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cw(0x12, 0x81); // NADC 1
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cw(0x13, 0x82); // MADC 2
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cw(0x13, 0x82); // MADC 2
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cw(0x14, 0x80); // OSR ADC 128
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cw(0x14, 0b10000000); // OSR ADC 128
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cw(0x3d, 0b00000001); // ADC PRB_R3 = 11, PRB_R2 = 10, PRB_R1 = 01
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//cw(0x14, 0b01000000); // OSR ADC 128
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cw(0x3d, 0b00000010); // ADC PRB_R3 = 11, PRB_R2 = 10, PRB_R1 = 01
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cw(0x00, 0x01); // select page 1
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cw(0x00, 0x01); // select page 1
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cw(0x3d, 0b01100100); // ADC PTM_R3
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cw(0x3d, 0b00000000); // ADC PTM_R4
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// DAC
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// DAC
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cw(0x00, 0x00); // select page 0
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cw(0x00, 0x00); // select page 0
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@ -136,24 +135,22 @@ void setup() {
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cw(0x0d, 0x00); // OSR DAC 128
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cw(0x0d, 0x00); // OSR DAC 128
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cw(0x0e, 0x80); // OSR DAC 128
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cw(0x0e, 0x80); // OSR DAC 128
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cw(0x1b, 0b00000000); // word length 16bits
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cw(0x1b, 0b00000000); // word length 16bits
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cw(0x3c, 0x08); // PRB_P8
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cw(0x3c, 0b00000011); // PRB_P3
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cw(0x00, 0x01); // select page 1
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cw(0x00, 0x01); // select page 1
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cw(0x7b, 0x01); // set REF charging time to 40ms
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cw(0x7b, 0b00000001); // set REF charging time to 40ms
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//cw(0x14, 0x25); // set HP soft stepping for anti pop
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//cw(0x0a, 0x0B); // set input CM to 0.9V and LO to 1.65V
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// ROUTING
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// ROUTING
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cw(0x00, 0x01); // select page 1
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cw(0x00, 0x01); // select page 1
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cw(0x0e, 0b00001000); // left DAC reconstruction filter routed to LOL
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cw(0x0e, 0b00001000); // left DAC reconstruction filter routed to LOL
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cw(0x0f, 0b00001000); // right DAC reconstruction filter routed to LOR
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cw(0x0f, 0b00001000); // right DAC reconstruction filter routed to LOR
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cw(0x03, 0b00000100); // DAC PTM_P3/4
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cw(0x03, 0b00000000); // DAC PTM_P3/4
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cw(0x04, 0b00000100); // DAC PTM_P3/4
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cw(0x04, 0b00000000); // DAC PTM_P3/4
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// LO GAIN
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// LO GAIN
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cw(0x00, 0x01);
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cw(0x00, 0x01);
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cw(0x12, 0b00000010); // LOL gain 0dB
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cw(0x12, 0b00000001); // LOL gain 0dB
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cw(0x13, 0b00000010); // LOR gain 0dB
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cw(0x13, 0b00000001); // LOR gain 0dB
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// POWER UP
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// POWER UP
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// ADC
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// ADC
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@ -183,8 +180,8 @@ void setup() {
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Serial.println("P0_42 - Sticky Flags");
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Serial.println("P0_42 - Sticky Flags");
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cr(0x2A, 1);
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cr(0x2A, 1);
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//i2s.onTransmit(codec_transmit);
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i2s.onTransmit(codec_transmit);
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//i2s.onReceive(codec_receive);
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i2s.onReceive(codec_receive);
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i2s.setDOUT(15);
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i2s.setDOUT(15);
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i2s.setDIN(14);
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i2s.setDIN(14);
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@ -195,7 +192,7 @@ void setup() {
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i2s.swapClocks();
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i2s.swapClocks();
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i2s.setBitsPerSample(16);
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i2s.setBitsPerSample(16);
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//i2s.setBuffers(6, SIZE * sizeof(int16_t) / sizeof(uint32_t));
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i2s.setBuffers(6, SIZE * sizeof(int16_t) / sizeof(uint32_t));
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if(!i2s.begin(48000)){
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if(!i2s.begin(48000)){
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Serial.println("I2S error!");
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Serial.println("I2S error!");
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@ -207,13 +204,13 @@ int32_t last = 0;
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int frame = 0;
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int frame = 0;
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void loop() {
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void loop() {
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int16_t l, r;
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int16_t l, r;
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i2s.read16(&l, &r);
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//i2s.read16(&l, &r);
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// float sine_pos = (2.0f * M_PI * 1000.0f * (float)frame) / (float)48000;
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// float sine_pos = (2.0f * M_PI * 1000.0f * (float)frame) / (float)48000;
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// l = (int16_t)(sin(sine_pos) * 8192.0f);
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// l = (int16_t)(sin(sine_pos) * 8192.0f);
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// r = l;
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// r = l;
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i2s.write16(l*-1, r*-1);
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//i2s.write16(l*-1, r*-1);
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// volume += l + r;
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// volume += l + r;
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// if(millis() - last > 1000){
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// if(millis() - last > 1000){
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