ui and sound together is almost ok but not quite there. occasional xruns

This commit is contained in:
Sebastian
2025-06-03 01:16:31 +02:00
parent ef52d50b7c
commit a1efe3cc10
4 changed files with 510 additions and 151 deletions

View File

@ -8,7 +8,7 @@
I2S i2s(INPUT_PULLUP);
TLV320AIC3204 codec;
TLV320AIC3204 codec;
#define SIZE 16
#define ECHO 192000
@ -59,105 +59,6 @@ void setup() {
digitalWrite(20, HIGH);
codec.begin(&Wire1);
/*
// GENERAL
cw(0x00, 0x00); // select page 0
cw(0x01, 0x01); // soft reset
cw(0x1b, 0b00000000); // select I2S with 16 bit word length
cw(0x1d, 0b00000000); // disable loopback
// POWER and CM
cw(0x00, 0x01); // select page 1
cw(0x01, 0b00001000); // disable weak (crude) AVdd connection to DVdd
cw(0x02, 0b00000001); // enable internal AVdd LDO and enable analog blocks
cw(0x09, 0b00001100); // power up LOL, LOR, power down MAL, MAR, HPL, HPR
cw(0x0a, 0b00001000); // set full chip CM to 0.75V
cw(0x47, 0b00110011); // analog input quick charge time 1.6ms
// ROUTING
cw(0x00, 0x01); // select page 1
cw(0x34, 0b10000000); // LEFT MICPGA P route IN1L to LEFT_P with 40k input impedance
//cw(0x36, 0b11000000); // LEFT MICPGA M route CM to LEFT_M with 20k input impedance
//cw(0x36, 0b00000011); // LEFT MICPGA M route CM to LEFT_M with 20k input impedance
cw(0x37, 0b10000000); // RIGHT MICPGA P route IN1R to RIGHT_P with 20k input impedance
//cw(0x39, 0b11000000); // RIGHT MICPGA M route CM to RIGHT_M with 20k input impedance
//cw(0x39, 0b00000011); // RIGHT MICPGA M route CM to RIGHT_M with 20k input impedance
cw(0x3a, 0b00111100); // connect IN2, IN3 weakly to CM
// GAIN
cw(0x00, 0x01); // select page 1
cw(0x3b, 0b00000000); // unmute left MICPGA, set gain to 0db
cw(0x3c, 0b00000000); // unmute right MICPGA, set gain to 0db
// VOLUME
cw(0x00, 0x01); // select page 1
cw(0x16, 0b01110101); // MUTE IN1L to HPL
cw(0x17, 0b01110101); // MUTE IN1R to HPR
// ADC
cw(0x00, 0x00); // select page 0
cw(0x12, 0x81); // NADC 1
cw(0x13, 0x82); // MADC 2
cw(0x14, 0b10000000); // OSR ADC 128
//cw(0x14, 0b01000000); // OSR ADC 128
cw(0x3d, 0b00000001); // ADC PRB_R3 = 11, PRB_R2 = 10, PRB_R1 = 01
cw(0x00, 0x01); // select page 1
cw(0x3d, 0b00000000); // ADC PTM_R4
// DAC
cw(0x00, 0x00); // select page 0
cw(0x0b, 0x81); // NDAC 1
cw(0x0c, 0x82); // MDAC 2
cw(0x0d, 0x00); // OSR DAC 128
cw(0x0e, 0x80); // OSR DAC 128
cw(0x1b, 0b00000000); // word length 16bits
cw(0x3c, 0b00000001); // PRB_P3
cw(0x00, 0x01); // select page 1
cw(0x7b, 0b00000001); // set REF charging time to 40ms
// ROUTING
cw(0x00, 0x01); // select page 1
cw(0x0e, 0b00001000); // left DAC reconstruction filter routed to LOL
cw(0x0f, 0b00001000); // right DAC reconstruction filter routed to LOR
cw(0x03, 0b00000000); // DAC PTM_P3/4
cw(0x04, 0b00000000); // DAC PTM_P3/4
// LO GAIN
cw(0x00, 0x01);
cw(0x12, 0b00000001); // LOL gain 0dB
cw(0x13, 0b00000001); // LOR gain 0dB
// POWER UP
// ADC
cw(0x00, 0x00); // select page 0
cw(0x51, 0b11000000); // power up ADC
cw(0x52, 0b00000000); // unmute ADC
cw(0x3f, 0b11010100); // power up and route left digital audio to left dac channel and right to right
cw(0x40, 0x00); // unmute DAC digital volume
// DAC VOLUME 0b00000000 = 0dB, 10000001 = -63.5dB, 0b00110000 = +24dB
cw(0x00, 0x00); // select page 0
cw(0x41, 0b11111001); // LEFT
cw(0x42, 0b11111001); // RIGHT
// ADC VOLUME 0b1101000 = -12dB, 0b00000000 = 0dB, 0b0101000 = +20dB
cw(0x00, 0x00); // select page 0
cw(0x53, 0b01110000); // LEFT
cw(0x54, 0b01110000); // RIGHT
// STATUS FLAGS
Serial.println("CODEC STATUS");
cw(0x00, 0x00); // select page 0
Serial.println("ADC Flags");
cr(0x24, 1);
Serial.println("DAC Flags");
cr(0x25, 1);
Serial.println("P0_42 - Sticky Flags");
cr(0x2A, 1);
*/
i2s.onTransmit(codec_transmit);
i2s.onReceive(codec_receive);